1. Field of the Invention
The present invention pertains to the field of switched networks and, especially, to data transmission in a switched network at high bit rates.
It may be recalled that switching enables the accurate routing of data between a source and one or more destinations, these data being organized in protocol data units and, for example, in packets.
2. Description of the Prior Art
In the prior art, two different switching techniques are known:                circuit switching; and        packet switching.        
A circuit switched network interconnecting several devices essentially uses Time Division Multiplexing or TDM. This technique enables synchronous data transmission by the allocation of time slots on the TDM bus to a variety of synchronous communications. At input, a source apparatus writes data on one or more time slots allocated to it. At output, one or more target apparatuses read the data in the time slot to which they are attached.
According to this technique, the time slots can be used as broadcasting channels. These broadcasting channels will be used in writing by only one source and in reading by several targets. Besides, the synchronous nature of the mechanism ensures that all the useful data will be suitably processed by all the apparatuses, both source and target.
In a packet switched network, the data transfer between the source apparatuses and the target apparatuses assumes that the network connecting them is available. In other words, it depends on the status of the network. Thus, a handshake type of protocol is provided to ensure not only that the data is available but also that it has been taken into account.
This is especially true when carrying out wormhole routing in which the data being transmitted can be distributed among several intermediate elements of the switching means (the decision to carry out a <<wormhole routing>> is taken before the complete reception of the packet, unlike in the case of <<store and forward routing>>) and/or when source and target apparatuses have FIFO (<<First In First Out>>) type buffer memories connected to both the source and the target ports.
This becomes even more critical in certain cases, especially when a target port has to cope with congestion, thus having a relatively lower bit rate at the output of a FIFO.
Besides, the packet switching technique does not allow for efficient multicast transmission (namely transmission from one source port to at least two target ports) except if costly and complicated switching matrixes known as <<crossbars>> are implemented.
The thesis report “Conception and realisation of high performance packet router”, Reube, 3rd Jul., 1997, describes a (8×8) wormhole switch relying on full crossbar implementation between parallel ports.
The multicast capability is addressed through slot labelling, as implemented for the C104 chip described in the U.S. Pat. No. 5,422,881 by Inmos Limited, and the patent U.S. Pat. No. 5,088,091 by DEC which illustrates the routing of the broadcasting through a routing table. Both solutions rely on crossbar switch implementation.
Today, in the prior art, there are no switched architecture buses in packet switching networks to provide simple and efficient multicast functions. Crossbar-based solutions exist but they remain complex and costly.
A first drawback of the prior art is that it cannot be used to carry out efficient switching in all circumstances, in optimizing the performance characteristics (par example, the bit rate for each communication or the total bit rate).
In particular, there are no techniques without <<crossbar>> switching that prove to be efficient and relatively inexpensive to implement;                when the switchings are applied to unicast type transmissions; and        when the switchings are applied efficiently to multicast type transmissions.        
Thus, the prior art systems generally favor multicast switching.
Another drawback is the fact that the prior art techniques using the “store and foreword routing” architecture have a high degree of latency and require greater memory capacity.
The invention according to its different aspects is aimed especially at overcoming these prior art drawbacks.
More specifically, it is a goal of the invention to provide a technique for multicast switching while enabling an optimum bit rate in the case of unicast transmission.
Furthermore, a call of the invention is to enable the performance of an “wormhole type routing” while minimizing the packet transfer latency both for unicast transmission and for multicast transmission.
It is yet another goal of the invention to provide an architecture that thus guarantees low-cost implementation and is a relatively uncomplicated to implement.